DFT 2008 - Call for Papers

CALL FOR PAPERS

Submission Deadline May 7, 2008!

Overview -- Author Information -- Contact -- Committees

Overview

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The topics include (but are not limited to) the following ones:

Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
Repair, Restructuring and Reconfiguration
Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on-line operation.
Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
Error Detection, Correction, and Recovery
Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy.
Defect and Fault Tolerance
Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults and errors.
Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization of IC and systems.
Emerging Technologies
DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors
Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine and space.

Author Information

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Prospective authors should prepare an extended summary or the full paper (up to 9 pages in the IEEE 6X9 format), to be submitted as PDF file. Uncompressed unencapsulated postscript may also be used when necessary. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:

http://www.dfts.org

We are also interested in panel sessions that involve industrial experiences: please send an email to the Program Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.

Paper Publication and Presenter Registration:
Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society.

Each accepted paper MUST have at least an author with a paid full registration for the manuscript to be included and published in the proceedings; an author is also expected to attend and present the paper at the Symposium.

Journal Special Issue:
Authors will have the opportunity to submit an extended version of their paper presented at the symposium in a special issue of an archival journal.

Best Paper Award:
A “Best Paper Award” will be awarded by the technical program committee.

Prospective authors should adhere to the following deadlines:

Submission deadline: May 7, 2008
Notification of acceptance: June 20, 2008
Camera ready full papers: July 14, 2008

For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.

Contact

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General Information

Cristiana Bolchini
Politecnico di Milano, ITALY
Phone: +39 02 2399 3619
E-mail: cristiana.bolchini@polimi.it

Yong-Bin Kim
Northeastern University, USA
Phone: +1 617 373 2919
E-mail: ybk@ece.neu.edu

Submission Information

Dimitris Gizopoulos
University of Piraeus, GREECE
Phone: +30 210 414 2372
E-mail: dgizop@unipi.gr

Mohammad Tehranipoor
University of Connecticut, USA
Phone: +1 860 486-3471
E-mail: tehrani@engr.uconn.edu

Committees

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General co-Chairs

Cristiana Bolchini
Politecnico di Milano, ITALY
Phone: +39 02 2399 3619
E-mail: cristiana.bolchini@polimi.it

Yong-Bin Kim
Northeastern University, USA
Phone: +1 617 373 2919
E-mail: ybk@ece.neu.edu

Program co-Chairs

Dimitris Gizopoulos
University of Piraeus, GREECE
Phone: +30 210 414 2372
E-mail: dgizop@unipi.gr

Mohammad Tehranipoor
University of Connecticut, USA
Phone: +1 860 486-3471
E-mail: tehrani@engr.uconn.edu

Publicity Chair

Marco Ottavi
Advanced Micro Devices, USA
E-mail: Marco.Ottavi@amd.com

Local Arrangements Chair

Harry Chen
MediaTek, USA
Email: Harry-H.Chen@mediatek.com

Program Committee
S. Chakravarty, LSI Logic
M. Choi, U. of Missouri Rolla
Y. Choi, Hongik U.
G. Chapman, Simon Fraser U.
R. Datta, TI
M. Favalli, U. of Ferrara
J. Figueras, U. Polit. Catalunya
E. Fujiwara, Tokyo Inst. of Tech.
M. Fukushi, Tohoku U.
S. Horiguchi, Tohoku U.
C. Huang, Nat'l Tsing Hua U.
H. Ito, Chiba U.
A. Jas , Intel
N. Jha, Princeton
W. Jone, U. of Cincinnati
I. Koren, UMASS Amherst
R. Leveugle, TIMA labs
J. Lo, U. of Rhode Island
F. Lombardi, Northeastern U.
Y. Makris, Yale
M. Margala, UMASS Lowell
I. Markov, U. of Michigan
C. Metra, U. of Bologna
Z. Navabi, Worcester Polyt. Inst.
N. Nicolici, McMaster U.
N. Park, Oklahoma State U.
A. Paschalis, U. of Athens
Z. Peng, Linkoping U.
W. Pleskacz, Warsaw U. T.
S. Pontarelli, U. of Rome "Tor Vergata"
J. Prashant, Intel
M. Rebaudengo, Politec. di Torino
S. Reddy, U. of Iowa
F. Salice, Politec. di Milano
A. Salsano, U. of Rome "Tor Vergata"
D. Sciuto, Politec. di Milano
S. Shukla, Virginia Tech
J. Teixeira, INESC-ID Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, U. of Texas at Austin
S. Tragoudas, Southern Ill. U.
R. Velazco, TIMA labs
M. Violante, Politec. di Torino
H. Walker, Texas A&M U.
L. Wang, U. of Commecticut
X. Wen, Kyushu Institute of Tech.
K. Zarrineh, AMD

For more information, visit us on the web at: http://www.dfts.org

The 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Fault-Tolerant Computing Technical Committee and Test Technology Technical Council (TTTC).